URL https://opencores.org/ocsvn/simpcon/simpcon/trunk

Subversion Repositories simpcon

[/] - Rev 23

Rev	Log message	Author	Age	Path
23	no message	martin	6107d 22h	/
22	update with Austrochip paper content and VHDL file descriptions	martin	6112d 11h	/
21	VHDL update	martin	6112d 12h	/
20	VHDL update	martin	6112d 14h	/
19	moved to JOP handbook	martin	6112d 14h	/
18	update from JOP	martin	6285d 13h	/
17	SimpCon - Wishbone bridge	martin	6735d 21h	/
16	Minimum SimpCon IO example	martin	6735d 21h	/
15	ISA bus example (used to connect the CS8900 Ethernet chip)	martin	6735d 21h	/
14	renamed to scio_min.vhd	martin	6735d 21h	/
13	no message	martin	6745d 01h	/
12	more IO examples	martin	6759d 00h	/
11	no message	martin	6759d 00h	/
10	Removed Flash ports	martin	6763d 16h	/
9	Generic decoding and data mux	martin	6765d 02h	/
8	Test IO slave and simple IO top	martin	6765d 04h	/
7	Changed signal names to use the names from the specification.	martin	6766d 20h	/
6	Signal section added	martin	6766d 23h	/
5	Add document sources to the project	martin	6766d 23h	/
4	A 32-bis static RAM slave with read pipeline level 2	martin	6767d 06h	/