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Rev Log message Author Age Path
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4275d 11h /
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs
jt_eaton 4310d 20h /
117 added yellow pages tools jt_eaton 4338d 15h /
116 added build_header
now use build_register for all spr components
resynced or1200 code back to use orbuild toolchain
jt_eaton 4373d 12h /
115 split or1200_cpu up into all ip-xact components
removed dead files
jt_eaton 4417d 17h /
114 moved or1200 connectivity out of verilog and into ip-xact
added or1200_boot block
removed force of 00 on lowest iwb_addr bits
jt_eaton 4429d 16h /
113 started refactoring or1200 jt_eaton 4435d 09h /
112 added more test sims
removed unneeded files
jt_eaton 4444d 21h /
111 split or1200 out into seperate test suite jt_eaton 4446d 16h /
110 split out more ip-xact components
added sw sources
jt_eaton 4458d 13h /
109 removed unused file jt_eaton 4461d 13h /
108 removed unneeded files jt_eaton 4462d 19h /
107 added designCfg files to all modules jt_eaton 4462d 22h /
106 checked in orp_soc project step 2 jt_eaton 4468d 15h /
105 moved or1200_monitor from testbench to dut jt_eaton 4471d 11h /
104 fixed search in preprocessor script
added initial orp_soc project
jt_eaton 4473d 12h /
103 added user guide
resynced to local repository
jt_eaton 4493d 13h /
102 all ip-xact files now readable by kactus2 jt_eaton 4555d 08h /
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT
jt_eaton 4556d 10h /
100 created workspace prroject=fpga_mrisc for single compile
general cleanup
jt_eaton 4568d 17h /

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