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Rev Log message Author Age Path
17 Define mess fixed. simons 7644d 18h /
16 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7644d 21h /
15 Defines set in order. simons 7644d 21h /
14 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7645d 15h /
13 8-bit WB access enabled. simons 7645d 15h /
12 Error fixed. simons 7665d 22h /
11 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7683d 21h /
10 Slave select signal generation bug fixed, default case added when reading registers, to avoid latches. simons 7683d 21h /
9 Support for 128 bits character length added. Zero value divider bug fixed. simons 7724d 15h /
8 Automatic slave select signal generation added. simons 7744d 16h /
7 Support for 64 bit caharacter len added. simons 7833d 04h /
6 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8001d 07h /
5 Document lectured. simons 8001d 07h /
4 PDF created. simons 8030d 22h /
3 This commit was manufactured by cvs2svn to create tag 'initial'. 8031d 16h /
2 Initial import simons 8031d 16h /
1 Standard project directories initialized by cvs2svn. 8031d 16h /

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