URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

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Rev	Log message	Author	Age	Path
68	lsr[7] was not showing overrun errors.	mohor	8202d 09h	/
67	Missing declaration of rf_push_q fixed.	mohor	8209d 09h	/
66	rx push changed to be only one cycle wide.	mohor	8209d 09h	/
65	Warnings fixed (unused signals removed).	mohor	8210d 14h	/
64	Warnings cleared.	mohor	8210d 15h	/
63	Synplicity was having troubles with the comment.	mohor	8210d 15h	/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8211d 14h	/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8212d 08h	/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8212d 12h	/
59	MSR register fixed.	mohor	8215d 09h	/
58	After reset modem status register MSR should be reset.	mohor	8215d 13h	/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8216d 12h	/
56	thre irq should be cleared only when being source of interrupt.	mohor	8216d 13h	/
55	some synthesis bugs fixed	gorban	8217d 00h	/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8217d 14h	/
53	Scratch register define added.	mohor	8218d 14h	/
52	Scratch register added	gorban	8219d 03h	/
51	Igor fixed break condition bugs	gorban	8219d 03h	/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8223d 08h	/
49	committed the debug interface file	gorban	8225d 01h	/

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Subversion Repositories uart16550

[/] - Rev 68

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