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Rev Log message Author Age Path
82 Updated to work with latest core. gorban 7995d 21h /
81 Added lastest additions. gorban 7995d 22h /
80 Remove uart_fifo.v because it is replaced by other 2 files. gorban 7995d 22h /
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7995d 22h /
78 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8149d 04h /
77 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 8149d 04h /
76 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 8149d 04h /
75 Endian define added. Big Byte Endian is selected by default. mohor 8149d 04h /
74 tf_overrun signal was disabled since it was not used gorban 8154d 05h /
73 major bug in 32-bit mode that prevented register access fixed. gorban 8161d 04h /
72 UART PHY added. Files are fully operational, working on HW. mohor 8174d 12h /
71 Removed confusing comment gorban 8186d 01h /
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8191d 09h /
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8200d 00h /
68 lsr[7] was not showing overrun errors. mohor 8203d 07h /
67 Missing declaration of rf_push_q fixed. mohor 8210d 07h /
66 rx push changed to be only one cycle wide. mohor 8210d 07h /
65 Warnings fixed (unused signals removed). mohor 8211d 12h /
64 Warnings cleared. mohor 8211d 13h /
63 Synplicity was having troubles with the comment. mohor 8211d 13h /

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