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Rev Log message Author Age Path
16 Lots of updates (see below)

New files:
1. AXI-lite formal checker(s)
2. AXI-lite to WB bridge
3. WB to AXI-lite bridge
4. WB cross bar (for lack of a better place)
5. Demonstration/example AXI-lite core

Other files have been updated as necessary. Ex. the WB formal checker files.		 dgisselq 1907d 21h /
15 Quick update, making this module verilatable again dgisselq 2268d 00h /
14 Added a reset line upon user request dgisselq 2268d 00h /
13 Bug fix release--fixes the bugs Antti pointed out. dgisselq 2280d 14h /
12 Added Verilators obj_dir to the list of ignored files dgisselq 2378d 01h /
11 Updated the bench/formal properties

SVN will now ignore the build files associated with this directory: *.smt2,
*.yslog, *.vcd		 dgisselq 2378d 01h /
10 Added files to flush out the formal proof capability dgisselq 2378d 01h /
9 Added a formal directory dgisselq 2378d 01h /
8 The WB to AXI translator wrks and works well.

A proof of this will be added shortly.		 dgisselq 2378d 01h /
7 Simplified. dgisselq 2695d 01h /
6 IT WORKS!!! (On non-pipelined data--havent tested it on pipelined stuff .. yet) dgisselq 2822d 21h /
5 Adjusted variable names to match the spec and the MIG. dgisselq 2827d 12h /
4 Adjusted the core quickly so it should work for 128-bit wide wishbone busses
as well as 32-bit wide busses.		 dgisselq 2827d 18h /
3 Fixed the Verilator compile-time bugs. Still haven't tested the core. dgisselq 2827d 18h /
2 Initial check in. Core not (yet) tested, verified, or validated. dgisselq 2827d 19h /
1 The project and the structure was created root 2827d 19h /

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