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Rev Log message Author Age Path
28 Adding parameter for max frame size antanguay 4159d 19h /
27 Fix octets stats on barrel shift transitions antanguay 4208d 19h /
26 Fix packet count antanguay 4214d 19h /
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4214d 20h /
24 Use FIFO's for statistics clock domain crossing antanguay 4214d 22h /
23 Adding basic packet stats antanguay 4215d 04h /
22 Added prototype system verilog testbench antanguay 4217d 01h /
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4217d 01h /
20 Updates for Xilinx synthesis antanguay 4506d 19h /
19 Updates for 32/64 bit systems antanguay 4681d 20h /
18 Updates for linux 32-bit antanguay 4682d 17h /
17 Fixed deprecated SystemC warnings antanguay 4685d 01h /
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4685d 07h /
15 Updated for Verilator 3.813 antanguay 4704d 08h /
14 Change interface to big endian, added serdes examples to testbench antanguay 5293d 02h /
13 Change interface to big endian, added serdes examples to testbench antanguay 5293d 03h /
12 Change interface to big endian, added serdes examples to testbench antanguay 5293d 03h /
11 Fixed clock crossing antanguay 5399d 00h /
10 Added details to spec antanguay 5496d 19h /
9 Added old uploaded documents to new repository. root 5571d 07h /

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