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Subversion Repositories xucpu

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Rev	Log message	Author	Age	Path
23	Currently moved test bench to 10 bit address. Created spreadsheet for filling memory with random data. When testing, memory is apparently not initialised.	lcdsgmtr	3167d 03h	/
22	Update on makefile, because some parts are in other files.	lcdsgmtr	3167d 03h	/
21	Since all BRAM is unified in one component, this testbench is not necessary anymore.	lcdsgmtr	3167d 03h	/
20	Update RAM package to allow for 15-bit address. Update test bench to use address width parameter.	lcdsgmtr	3167d 03h	/
19	Makefile for building memory block testbench.	lcdsgmtr	3167d 03h	/
18	Ignore work files from GHDL.	lcdsgmtr	3167d 03h	/
17	Moving the generic block ram component piece by piece to a better implementation.	lcdsgmtr	3167d 03h	/
16	Re-write of memory in function of initial array memory blocks.	lcdsgmtr	3167d 03h	/
15	Unification of all RAM parts into one interface.	lcdsgmtr	3167d 03h	/
14	Simple implementation project.	lcdsgmtr	3299d 01h	/
13	Updated smallest Xilinx configuration.	lcdsgmtr	3299d 01h	/
12	Update Xilinx configurations.	lcdsgmtr	3299d 01h	/
11	Successful run of the simulation. Correct results.	lcdsgmtr	3299d 03h	/
10	Correct build with GHDL.	lcdsgmtr	3299d 03h	/
9	This makes sure that this GHDL configuration analyses correctly.	lcdsgmtr	3299d 03h	/
8	Rebuilding the configuration to build the first system using GHDL.	lcdsgmtr	3300d 02h	/
7	Moved package for initialising memory also to src.	lcdsgmtr	3300d 02h	/
6	Removed some unnecessary files and directories. Moved other files to new directories.	lcdsgmtr	3300d 02h	/
5	Re-organisation of repository.	lcdsgmtr	3301d 03h	/
4	Added directories for guiding implementation using Xilinx ISE and GHDL.	lcdsgmtr	3336d 03h	/

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Subversion Repositories xucpu

[/] - Rev 23

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