URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [bench/] - Rev 157

Rev	Log message	Author	Age	Path
157	change data output.	simont	7682d 22h	/8051/trunk/bench/
156	add FREQ paremeter.	simont	7682d 22h	/8051/trunk/bench/
155	add aditional tests.	simont	7682d 22h	/8051/trunk/bench/
130	prepared programs for new timing.	simont	7723d 16h	/8051/trunk/bench/
129	updated...	simont	7723d 16h	/8051/trunk/bench/
125	update, add prescaler, rclk, tclk.	simont	7732d 23h	/8051/trunk/bench/
124	add support for external rom from xilinx ramb4	simont	7732d 23h	/8051/trunk/bench/
120	defines for pherypherals added	simont	7738d 20h	/8051/trunk/bench/
111	Remove instruction cache and wb_interface	simont	7745d 14h	/8051/trunk/bench/
103	rename signals	simont	7746d 18h	/8051/trunk/bench/
97	initial inport	simont	7746d 21h	/8051/trunk/bench/
96	initial import	simont	7746d 21h	/8051/trunk/bench/
84	remove wb_bus_mon	simont	7825d 18h	/8051/trunk/bench/
74	add module oc8051_wb_iinterface	simont	7902d 16h	/8051/trunk/bench/
68	add instruction cache and DELAY parameters for external ram, rom	simont	7906d 19h	/8051/trunk/bench/
59	add external rom	simont	7913d 14h	/8051/trunk/bench/
46	prepared header	simont	7930d 16h	/8051/trunk/bench/
37	added signals ack, stb and cyc	simont	7957d 18h	/8051/trunk/bench/
4	Code repaired to satisfy the linter; testbech fails	markom	7977d 22h	/8051/trunk/bench/
2	Initial CVS import	simont	7993d 20h	/8051/trunk/bench/