URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] - Rev 177

Rev	Log message	Author	Age	Path
177	Fix bug in case of writing and reading from same address.	simont	7659d 17h	/8051/trunk/rtl/
175	initial inport.	simont	7659d 19h	/8051/trunk/rtl/
174	ram modules added.	simont	7659d 19h	/8051/trunk/rtl/
173	simualtion `ifdef added	simont	7659d 19h	/8051/trunk/rtl/
172	BIST signals added.	simont	7662d 18h	/8051/trunk/rtl/
171	fix bug in DA operation.	simont	7670d 16h	/8051/trunk/rtl/
158	fix bug.	simont	7674d 21h	/8051/trunk/rtl/
153	`ifdef added.	simont	7676d 15h	/8051/trunk/rtl/
152	sub_result output added.	simont	7676d 15h	/8051/trunk/rtl/
151	remove pc_r register.	simont	7676d 15h	/8051/trunk/rtl/
150	fix some bugs.	simont	7676d 15h	/8051/trunk/rtl/
149	pipelined acces to axternal instruction interface added.	simont	7676d 16h	/8051/trunk/rtl/
148	include "8051_defines" added.	simont	7676d 16h	/8051/trunk/rtl/
146	fix bug in movc intruction.	simont	7698d 16h	/8051/trunk/rtl/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7703d 20h	/8051/trunk/rtl/
144	chsnge comp.des to des1	simont	7703d 20h	/8051/trunk/rtl/
143	add wire sub_result, conect it to des_acc and des1.	simont	7703d 20h	/8051/trunk/rtl/
142	optimize state machine.	simont	7704d 22h	/8051/trunk/rtl/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7704d 23h	/8051/trunk/rtl/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7704d 23h	/8051/trunk/rtl/