URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 117

Rev	Log message	Author	Age	Path
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7730d 22h	/8051/trunk/rtl/verilog/
116	change sfr's interface.	simont	7732d 23h	/8051/trunk/rtl/verilog/
115	change uart to meet timing.	simont	7733d 00h	/8051/trunk/rtl/verilog/
114	remove t2mod register	simont	7736d 03h	/8051/trunk/rtl/verilog/
113	signal prsc_ow added.	simont	7736d 03h	/8051/trunk/rtl/verilog/
112	change timers to meet timing specifications (add divider with 12)	simont	7736d 03h	/8051/trunk/rtl/verilog/
110	change adr_i and adr_o length.	simont	7736d 18h	/8051/trunk/rtl/verilog/
109	add `include "oc8051_defines.v"	simont	7736d 18h	/8051/trunk/rtl/verilog/
108	fix some bugs, use oc8051_cache_ram.	simont	7736d 19h	/8051/trunk/rtl/verilog/
107	Include instruction cache.	simont	7736d 19h	/8051/trunk/rtl/verilog/
105	generic_dpram used	simont	7737d 22h	/8051/trunk/rtl/verilog/
104	use generic_dpram	simont	7737d 22h	/8051/trunk/rtl/verilog/
102	raname signals.	simont	7737d 23h	/8051/trunk/rtl/verilog/
95	updating...	simont	7738d 02h	/8051/trunk/rtl/verilog/
94	fix bug.	simont	7738d 02h	/8051/trunk/rtl/verilog/
93	OC8051_XILINX_RAM added	simont	7738d 02h	/8051/trunk/rtl/verilog/
92	initial inport	simont	7738d 02h	/8051/trunk/rtl/verilog/
90	change module name.	simont	7742d 20h	/8051/trunk/rtl/verilog/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7803d 23h	/8051/trunk/rtl/verilog/
88	fix bugs	simont	7809d 00h	/8051/trunk/rtl/verilog/