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[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 133

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Rev Log message Author Age Path
133 fix bug in substraction. simont 7711d 05h /8051/trunk/rtl/verilog/
132 change branch instruction execution (reduse needed clock periods). simont 7714d 20h /8051/trunk/rtl/verilog/
128 chance idat_ir to 24 bit wide simont 7724d 03h /8051/trunk/rtl/verilog/
127 fix bug (cyc_o and stb_o) simont 7724d 03h /8051/trunk/rtl/verilog/
126 define OC8051_XILINX_RAMB added simont 7724d 03h /8051/trunk/rtl/verilog/
123 fiz bug iv pcs operation. simont 7725d 23h /8051/trunk/rtl/verilog/
122 deifne OC8051_ROM added simont 7729d 03h /8051/trunk/rtl/verilog/
121 Change pc add value from 23'h to 16'h simont 7729d 03h /8051/trunk/rtl/verilog/
120 defines for pherypherals added simont 7730d 00h /8051/trunk/rtl/verilog/
119 remove signal sbuf_txd [12:11] simont 7730d 04h /8051/trunk/rtl/verilog/
118 change wr_sft to 2 bit wire. simont 7730d 21h /8051/trunk/rtl/verilog/
117 Register oc8051_sfr dato output, add signal wait_data. simont 7730d 21h /8051/trunk/rtl/verilog/
116 change sfr's interface. simont 7732d 22h /8051/trunk/rtl/verilog/
115 change uart to meet timing. simont 7733d 00h /8051/trunk/rtl/verilog/
114 remove t2mod register simont 7736d 03h /8051/trunk/rtl/verilog/
113 signal prsc_ow added. simont 7736d 03h /8051/trunk/rtl/verilog/
112 change timers to meet timing specifications (add divider with 12) simont 7736d 03h /8051/trunk/rtl/verilog/
110 change adr_i and adr_o length. simont 7736d 18h /8051/trunk/rtl/verilog/
109 add `include "oc8051_defines.v" simont 7736d 18h /8051/trunk/rtl/verilog/
108 fix some bugs, use oc8051_cache_ram. simont 7736d 18h /8051/trunk/rtl/verilog/

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