URL https://opencores.org/ocsvn/8051/8051/trunk

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[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 139

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Rev	Log message	Author	Age	Path
139	add aditional alu destination to solve critical path.	simont	7705d 12h	/8051/trunk/rtl/verilog/
138	Change buffering to save one clock per instruction.	simont	7705d 12h	/8051/trunk/rtl/verilog/
137	change to fit xrom.	simont	7705d 18h	/8051/trunk/rtl/verilog/
136	registering outputs.	simont	7705d 18h	/8051/trunk/rtl/verilog/
135	prepared start of receiving if ren is not active.	simont	7711d 17h	/8051/trunk/rtl/verilog/
134	fix bug in case execution of two data dependent instructions.	simont	7711d 17h	/8051/trunk/rtl/verilog/
133	fix bug in substraction.	simont	7711d 20h	/8051/trunk/rtl/verilog/
132	change branch instruction execution (reduse needed clock periods).	simont	7715d 11h	/8051/trunk/rtl/verilog/
128	chance idat_ir to 24 bit wide	simont	7724d 18h	/8051/trunk/rtl/verilog/
127	fix bug (cyc_o and stb_o)	simont	7724d 18h	/8051/trunk/rtl/verilog/
126	define OC8051_XILINX_RAMB added	simont	7724d 18h	/8051/trunk/rtl/verilog/
123	fiz bug iv pcs operation.	simont	7726d 14h	/8051/trunk/rtl/verilog/
122	deifne OC8051_ROM added	simont	7729d 18h	/8051/trunk/rtl/verilog/
121	Change pc add value from 23'h to 16'h	simont	7729d 18h	/8051/trunk/rtl/verilog/
120	defines for pherypherals added	simont	7730d 15h	/8051/trunk/rtl/verilog/
119	remove signal sbuf_txd [12:11]	simont	7730d 19h	/8051/trunk/rtl/verilog/
118	change wr_sft to 2 bit wire.	simont	7731d 12h	/8051/trunk/rtl/verilog/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7731d 12h	/8051/trunk/rtl/verilog/
116	change sfr's interface.	simont	7733d 13h	/8051/trunk/rtl/verilog/
115	change uart to meet timing.	simont	7733d 15h	/8051/trunk/rtl/verilog/

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Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 139

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