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[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 150

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Rev Log message Author Age Path
150 fix some bugs. simont 7677d 05h /8051/trunk/rtl/verilog/
149 pipelined acces to axternal instruction interface added. simont 7677d 05h /8051/trunk/rtl/verilog/
148 include "8051_defines" added. simont 7677d 06h /8051/trunk/rtl/verilog/
146 fix bug in movc intruction. simont 7699d 06h /8051/trunk/rtl/verilog/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7704d 10h /8051/trunk/rtl/verilog/
144 chsnge comp.des to des1 simont 7704d 10h /8051/trunk/rtl/verilog/
143 add wire sub_result, conect it to des_acc and des1. simont 7704d 10h /8051/trunk/rtl/verilog/
142 optimize state machine. simont 7705d 11h /8051/trunk/rtl/verilog/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7705d 13h /8051/trunk/rtl/verilog/
140 cahnge assigment to pc_wait (remove istb_o) simont 7705d 13h /8051/trunk/rtl/verilog/
139 add aditional alu destination to solve critical path. simont 7706d 07h /8051/trunk/rtl/verilog/
138 Change buffering to save one clock per instruction. simont 7706d 07h /8051/trunk/rtl/verilog/
137 change to fit xrom. simont 7706d 12h /8051/trunk/rtl/verilog/
136 registering outputs. simont 7706d 12h /8051/trunk/rtl/verilog/
135 prepared start of receiving if ren is not active. simont 7712d 11h /8051/trunk/rtl/verilog/
134 fix bug in case execution of two data dependent instructions. simont 7712d 11h /8051/trunk/rtl/verilog/
133 fix bug in substraction. simont 7712d 14h /8051/trunk/rtl/verilog/
132 change branch instruction execution (reduse needed clock periods). simont 7716d 05h /8051/trunk/rtl/verilog/
128 chance idat_ir to 24 bit wide simont 7725d 12h /8051/trunk/rtl/verilog/
127 fix bug (cyc_o and stb_o) simont 7725d 13h /8051/trunk/rtl/verilog/

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