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URL https://opencores.org/ocsvn/8051/8051/trunk

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[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 173

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Rev Log message Author Age Path
173 simualtion `ifdef added simont 7659d 12h /8051/trunk/rtl/verilog/
172 BIST signals added. simont 7662d 11h /8051/trunk/rtl/verilog/
171 fix bug in DA operation. simont 7670d 08h /8051/trunk/rtl/verilog/
158 fix bug. simont 7674d 14h /8051/trunk/rtl/verilog/
153 `ifdef added. simont 7676d 08h /8051/trunk/rtl/verilog/
152 sub_result output added. simont 7676d 08h /8051/trunk/rtl/verilog/
151 remove pc_r register. simont 7676d 08h /8051/trunk/rtl/verilog/
150 fix some bugs. simont 7676d 08h /8051/trunk/rtl/verilog/
149 pipelined acces to axternal instruction interface added. simont 7676d 08h /8051/trunk/rtl/verilog/
148 include "8051_defines" added. simont 7676d 08h /8051/trunk/rtl/verilog/
146 fix bug in movc intruction. simont 7698d 09h /8051/trunk/rtl/verilog/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7703d 13h /8051/trunk/rtl/verilog/
144 chsnge comp.des to des1 simont 7703d 13h /8051/trunk/rtl/verilog/
143 add wire sub_result, conect it to des_acc and des1. simont 7703d 13h /8051/trunk/rtl/verilog/
142 optimize state machine. simont 7704d 14h /8051/trunk/rtl/verilog/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7704d 16h /8051/trunk/rtl/verilog/
140 cahnge assigment to pc_wait (remove istb_o) simont 7704d 16h /8051/trunk/rtl/verilog/
139 add aditional alu destination to solve critical path. simont 7705d 09h /8051/trunk/rtl/verilog/
138 Change buffering to save one clock per instruction. simont 7705d 09h /8051/trunk/rtl/verilog/
137 change to fit xrom. simont 7705d 15h /8051/trunk/rtl/verilog/

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