URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 29

Rev	Log message	Author	Age	Path
29	fix some bugs	simont	7955d 04h	/8051/trunk/rtl/verilog/
28	remove syn signal	simont	7955d 04h	/8051/trunk/rtl/verilog/
27	fix some bugs	simont	7955d 04h	/8051/trunk/rtl/verilog/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7955d 06h	/8051/trunk/rtl/verilog/
25	divider and multiplier pass test	markom	7956d 01h	/8051/trunk/rtl/verilog/
23	mul & div use 4 clocks	simont	7956d 20h	/8051/trunk/rtl/verilog/
22	fix some bugs	simont	7956d 20h	/8051/trunk/rtl/verilog/
21	mul bug fixed	markom	7957d 01h	/8051/trunk/rtl/verilog/
20	multiplier and divider changed so they complete in 4 cycles	markom	7957d 04h	/8051/trunk/rtl/verilog/
19	combinatorial loop removed	simont	7957d 20h	/8051/trunk/rtl/verilog/
17	fix some bugs	simont	7961d 02h	/8051/trunk/rtl/verilog/
16	inputs ram and op2 removed	simont	7961d 02h	/8051/trunk/rtl/verilog/
15	commbinatorial loop removed	simont	7961d 02h	/8051/trunk/rtl/verilog/
13	some bug fix	simont	7962d 00h	/8051/trunk/rtl/verilog/
12	des1_r in alu port list	simont	7962d 00h	/8051/trunk/rtl/verilog/
11	des2_r removed	simont	7962d 00h	/8051/trunk/rtl/verilog/
10	% replaced with ^ in uart; some minor improvements	markom	7962d 06h	/8051/trunk/rtl/verilog/
9	removed unused compare states	markom	7963d 23h	/8051/trunk/rtl/verilog/
8	some IDS optimizations	markom	7963d 23h	/8051/trunk/rtl/verilog/
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	7964d 00h	/8051/trunk/rtl/verilog/