URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 32

Rev	Log message	Author	Age	Path
32	overflow repaired	simont	7960d 02h	/8051/trunk/rtl/verilog/
31	fix some bugs	simont	7966d 18h	/8051/trunk/rtl/verilog/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	7970d 00h	/8051/trunk/rtl/verilog/
29	fix some bugs	simont	7970d 01h	/8051/trunk/rtl/verilog/
28	remove syn signal	simont	7970d 01h	/8051/trunk/rtl/verilog/
27	fix some bugs	simont	7970d 01h	/8051/trunk/rtl/verilog/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7970d 03h	/8051/trunk/rtl/verilog/
25	divider and multiplier pass test	markom	7970d 22h	/8051/trunk/rtl/verilog/
23	mul & div use 4 clocks	simont	7971d 17h	/8051/trunk/rtl/verilog/
22	fix some bugs	simont	7971d 17h	/8051/trunk/rtl/verilog/
21	mul bug fixed	markom	7971d 22h	/8051/trunk/rtl/verilog/
20	multiplier and divider changed so they complete in 4 cycles	markom	7972d 01h	/8051/trunk/rtl/verilog/
19	combinatorial loop removed	simont	7972d 17h	/8051/trunk/rtl/verilog/
17	fix some bugs	simont	7975d 23h	/8051/trunk/rtl/verilog/
16	inputs ram and op2 removed	simont	7975d 23h	/8051/trunk/rtl/verilog/
15	commbinatorial loop removed	simont	7975d 23h	/8051/trunk/rtl/verilog/
13	some bug fix	simont	7976d 21h	/8051/trunk/rtl/verilog/
12	des1_r in alu port list	simont	7976d 21h	/8051/trunk/rtl/verilog/
11	des2_r removed	simont	7976d 21h	/8051/trunk/rtl/verilog/
10	% replaced with ^ in uart; some minor improvements	markom	7977d 03h	/8051/trunk/rtl/verilog/