URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 40

Rev	Log message	Author	Age	Path
40	added sigals for interacting with external ram	simont	7935d 09h	/8051/trunk/rtl/verilog/
38	fix some bugs	simont	7942d 07h	/8051/trunk/rtl/verilog/
37	added signals ack, stb and cyc	simont	7942d 07h	/8051/trunk/rtl/verilog/
36	fix bugs in mode 0	simont	7942d 07h	/8051/trunk/rtl/verilog/
32	overflow repaired	simont	7943d 12h	/8051/trunk/rtl/verilog/
31	fix some bugs	simont	7950d 04h	/8051/trunk/rtl/verilog/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	7953d 10h	/8051/trunk/rtl/verilog/
29	fix some bugs	simont	7953d 11h	/8051/trunk/rtl/verilog/
28	remove syn signal	simont	7953d 11h	/8051/trunk/rtl/verilog/
27	fix some bugs	simont	7953d 12h	/8051/trunk/rtl/verilog/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7953d 13h	/8051/trunk/rtl/verilog/
25	divider and multiplier pass test	markom	7954d 08h	/8051/trunk/rtl/verilog/
23	mul & div use 4 clocks	simont	7955d 03h	/8051/trunk/rtl/verilog/
22	fix some bugs	simont	7955d 03h	/8051/trunk/rtl/verilog/
21	mul bug fixed	markom	7955d 08h	/8051/trunk/rtl/verilog/
20	multiplier and divider changed so they complete in 4 cycles	markom	7955d 11h	/8051/trunk/rtl/verilog/
19	combinatorial loop removed	simont	7956d 03h	/8051/trunk/rtl/verilog/
17	fix some bugs	simont	7959d 09h	/8051/trunk/rtl/verilog/
16	inputs ram and op2 removed	simont	7959d 09h	/8051/trunk/rtl/verilog/
15	commbinatorial loop removed	simont	7959d 09h	/8051/trunk/rtl/verilog/