URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 78

Rev	Log message	Author	Age	Path
78	alu with registered outputs	simont	7870d 09h	/8051/trunk/rtl/verilog/
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7879d 06h	/8051/trunk/rtl/verilog/
76	add module oc8051_sfr, 256 bytes internal ram	simont	7879d 06h	/8051/trunk/rtl/verilog/
75	initial import	simont	7879d 06h	/8051/trunk/rtl/verilog/
73	initial import	simont	7887d 07h	/8051/trunk/rtl/verilog/
72	fix bug in interface to external data ram	simont	7887d 08h	/8051/trunk/rtl/verilog/
67	add parameters for instruction cache	simont	7891d 10h	/8051/trunk/rtl/verilog/
62	fix bugs in instruction interface	simont	7892d 06h	/8051/trunk/rtl/verilog/
54	cahnge interface to instruction rom	simont	7898d 04h	/8051/trunk/rtl/verilog/
47	remove unused files	simont	7915d 06h	/8051/trunk/rtl/verilog/
46	prepared header	simont	7915d 06h	/8051/trunk/rtl/verilog/
45	prepared header	simont	7915d 06h	/8051/trunk/rtl/verilog/
44	prepared header	simont	7915d 07h	/8051/trunk/rtl/verilog/
41	remove unused files	simont	7915d 08h	/8051/trunk/rtl/verilog/
40	added sigals for interacting with external ram	simont	7935d 10h	/8051/trunk/rtl/verilog/
38	fix some bugs	simont	7942d 08h	/8051/trunk/rtl/verilog/
37	added signals ack, stb and cyc	simont	7942d 08h	/8051/trunk/rtl/verilog/
36	fix bugs in mode 0	simont	7942d 08h	/8051/trunk/rtl/verilog/
32	overflow repaired	simont	7943d 13h	/8051/trunk/rtl/verilog/
31	fix some bugs	simont	7950d 05h	/8051/trunk/rtl/verilog/