URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] - Rev 44

Rev	Log message	Author	Age	Path
44	Add single step support	ultra_embedded	3681d 22h	/altor32/trunk/rtl/
40	- Add support for 2 way instruction cache (not yet enabled) - Bug fixes and tidy up	ultra_embedded	3696d 01h	/altor32/trunk/rtl/
39	Bug fix interrupt handling after last update.	ultra_embedded	3700d 21h	/altor32/trunk/rtl/
37	- Add icarus sim test - Adopt consistent naming scheme - Simplify instruction cache	ultra_embedded	3710d 06h	/altor32/trunk/rtl/
36	Various performance improvements and bug fixes.	ultra_embedded	3715d 19h	/altor32/trunk/rtl/
34	Add cutdown non-pipelined version of core.	ultra_embedded	3739d 04h	/altor32/trunk/rtl/
32	Switch memory interfaces to Wishbone (pipelined). Various bug fixes and improvements.	ultra_embedded	3808d 23h	/altor32/trunk/rtl/
31	Improvements to the execute stage logic.	ultra_embedded	3828d 23h	/altor32/trunk/rtl/
30	Fix verilog issues which break in XST.	ultra_embedded	3913d 02h	/altor32/trunk/rtl/
27	Initial drop of AltOR32 v2	ultra_embedded	3913d 22h	/altor32/trunk/rtl/