URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] - Rev 63

Rev	Log message	Author	Age	Path
63	Add support for Xilinx ISim Verilog simulator. Remove Virtex-6 files.	csantifort	4065d 20h	/amber/trunk/hw/vlog/amber23/
58	Use TB.clk_count for the decompiler messages and removed the local counter	csantifort	4640d 12h	/amber/trunk/hw/vlog/amber23/
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4657d 11h	/amber/trunk/hw/vlog/amber23/
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4672d 09h	/amber/trunk/hw/vlog/amber23/
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	4745d 11h	/amber/trunk/hw/vlog/amber23/
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	4763d 08h	/amber/trunk/hw/vlog/amber23/
15	Copied amber to amber23, Many system changes to support new amber25 core.	csantifort	4865d 04h	/amber/trunk/hw/vlog/amber23/
2	Baseline release of the Amber 2 core	csantifort	4895d 14h	/amber/trunk/hw/vlog/amber/