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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] - Rev 82

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Rev Log message Author Age Path
82 Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug csantifort 3371d 08h /amber/trunk/hw/vlog/amber25/
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.		 csantifort 4057d 20h /amber/trunk/hw/vlog/amber25/
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4562d 11h /amber/trunk/hw/vlog/amber25/
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4632d 12h /amber/trunk/hw/vlog/amber25/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 4649d 12h /amber/trunk/hw/vlog/amber25/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4664d 10h /amber/trunk/hw/vlog/amber25/
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly		 csantifort 4762d 10h /amber/trunk/hw/vlog/amber25/
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4764d 09h /amber/trunk/hw/vlog/amber25/
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts		 csantifort 4765d 16h /amber/trunk/hw/vlog/amber25/
30 Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays csantifort 4781d 16h /amber/trunk/hw/vlog/amber25/
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.		 csantifort 4850d 16h /amber/trunk/hw/vlog/amber25/
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions		 csantifort 4854d 14h /amber/trunk/hw/vlog/amber25/
16 Deleted the old version of the 3-state amber core. Its replaced with amber23.
Added the 5-state Amber core.		 csantifort 4857d 04h /amber/trunk/hw/vlog/amber25/

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