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[/] [async_sdm_noc/] - Rev 79

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Rev Log message Author Age Path
79 update comments in sim compile.sh to clarify that synthesis must be done before post-synthesis simulation wsong0210 4535d 10h /async_sdm_noc/
78 pass link wsong0210 4701d 22h /async_sdm_noc/
77 pass syn elaboration wsong0210 4702d 21h /async_sdm_noc/
76 fix syntex wsong0210 4706d 22h /async_sdm_noc/
75 code finished, start the debugging wsong0210 4706d 22h /async_sdm_noc/
74 in/out buffer finished wsong0210 4707d 22h /async_sdm_noc/
73 input buffer wsong0210 4714d 21h /async_sdm_noc/
72 clos-opt ongoing, Clos switch finished, nxt input buffer wsong0210 4715d 21h /async_sdm_noc/
71 the buffered 2-stage Clos switch wsong0210 4716d 21h /async_sdm_noc/
70 clos-opt ongoing wsong0210 4716d 21h /async_sdm_noc/
69 central module of the Clos wsong0210 4719d 21h /async_sdm_noc/
68 rewite the clos switch in the SDM-Clos-buf router wsong0210 4720d 22h /async_sdm_noc/
67 structure not good, prepare to use new files wsong0210 4720d 23h /async_sdm_noc/
66 clos opt ongoing wsong0210 4735d 16h /async_sdm_noc/
65 pipeline controller wsong0210 4735d 16h /async_sdm_noc/
64 clos opt ongoing wsong0210 4735d 16h /async_sdm_noc/
63 clos opt ongoing wsong0210 4735d 21h /async_sdm_noc/
62 clos opt ongoing wsong0210 4736d 22h /async_sdm_noc/
61 settle down the pipeline controller wsong0210 4741d 21h /async_sdm_noc/
60 try to make the address comparison relaxed QDI wsong0210 4744d 22h /async_sdm_noc/

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