URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] - Rev 12

Rev	Log message	Author	Age	Path
12	Added timing information to the capture content.	ash_riple	4453d 09h	/bustap-jtag/trunk/
11	Added pre-trigger capture.	ash_riple	4454d 01h	/bustap-jtag/trunk/
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4459d 06h	/bustap-jtag/trunk/
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4460d 01h	/bustap-jtag/trunk/
8	Added fault handling of wrong input length in the GUI.	ash_riple	4464d 01h	/bustap-jtag/trunk/
7	Added references related to "Bus Monitor".	ash_riple	4464d 05h	/bustap-jtag/trunk/
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4465d 01h	/bustap-jtag/trunk/
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4468d 02h	/bustap-jtag/trunk/
3	Added original article.	ash_riple	4468d 04h	/bustap-jtag/trunk/
2	Checked in working code base.	ash_riple	4472d 01h	/bustap-jtag/trunk/
1	The project and the structure was created	root	4472d 15h	/bustap-jtag/trunk/