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URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] - Rev 17

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Rev	Log message	Author	Age	Path
17	Added unreachable trigger condition "@WR & @RD" checking.	ash_riple	4419d 15h	/bustap-jtag/trunk/
15	Released version 2.2.	ash_riple	4441d 15h	/bustap-jtag/trunk/
14	Changed dec to hex value of triggerPnum.	ash_riple	4442d 06h	/bustap-jtag/trunk/
13	Added minor syntax changes and Linux environment simulation script.	ash_riple	4442d 12h	/bustap-jtag/trunk/
12	Added timing information to the capture content.	ash_riple	4442d 19h	/bustap-jtag/trunk/
11	Added pre-trigger capture.	ash_riple	4443d 11h	/bustap-jtag/trunk/
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4448d 16h	/bustap-jtag/trunk/
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4449d 11h	/bustap-jtag/trunk/
8	Added fault handling of wrong input length in the GUI.	ash_riple	4453d 11h	/bustap-jtag/trunk/
7	Added references related to "Bus Monitor".	ash_riple	4453d 15h	/bustap-jtag/trunk/
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4454d 11h	/bustap-jtag/trunk/
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4457d 12h	/bustap-jtag/trunk/
3	Added original article.	ash_riple	4457d 14h	/bustap-jtag/trunk/
2	Checked in working code base.	ash_riple	4461d 11h	/bustap-jtag/trunk/
1	The project and the structure was created	root	4462d 01h	/bustap-jtag/trunk/

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