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Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] - Rev 22

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Rev Log message Author Age Path
20 Added support for 32bit Address bus. ash_riple 3770d 13h /bustap-jtag/trunk/
19 Minor changes. ash_riple 4184d 07h /bustap-jtag/trunk/
18 Added support for Xilinx Chips.
Added support for AXI4-Lite bus. Can be used as an XPS IP.
ash_riple 4184d 08h /bustap-jtag/trunk/
17 Added unreachable trigger condition "@WR & @RD" checking. ash_riple 4430d 11h /bustap-jtag/trunk/
15 Released version 2.2. ash_riple 4452d 11h /bustap-jtag/trunk/
14 Changed dec to hex value of triggerPnum. ash_riple 4453d 02h /bustap-jtag/trunk/
13 Added minor syntax changes and Linux environment simulation script. ash_riple 4453d 08h /bustap-jtag/trunk/
12 Added timing information to the capture content. ash_riple 4453d 15h /bustap-jtag/trunk/
11 Added pre-trigger capture. ash_riple 4454d 07h /bustap-jtag/trunk/
10 Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure. ash_riple 4459d 12h /bustap-jtag/trunk/
9 Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do".
Virtual JTAG stimulus can only be entered statically before simulation starts.
FIFO operation can be simulated dynamically while simulation is run.
ash_riple 4460d 07h /bustap-jtag/trunk/
8 Added fault handling of wrong input length in the GUI. ash_riple 4464d 07h /bustap-jtag/trunk/
7 Added references related to "Bus Monitor". ash_riple 4464d 11h /bustap-jtag/trunk/
6 Updated to 2.1. New features added as in doc/Revision History.txt. ash_riple 4465d 07h /bustap-jtag/trunk/
5 Created code base for 2.x development.
Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.
ash_riple 4468d 08h /bustap-jtag/trunk/
3 Added original article. ash_riple 4468d 10h /bustap-jtag/trunk/
2 Checked in working code base. ash_riple 4472d 07h /bustap-jtag/trunk/
1 The project and the structure was created root 4472d 21h /bustap-jtag/trunk/

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