URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] [c16/] [tags/] [Rev_XLNX_5/] [vhdl/] - Rev 26

Rev	Log message	Author	Age	Path
26	New directory structure.	root	5576d 00h	/c16/tags/Rev_XLNX_5/vhdl/
20	This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_5'.		7131d 06h	/c16/tags/Rev_XLNX_5/vhdl/
19	FPGA Pin desription added.	jsauermann	7131d 06h	/c16/tags/Rev_XLNX_5/vhdl/
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7432d 05h	/c16/tags/Rev_XLNX_5/vhdl/
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7432d 05h	/c16/tags/Rev_XLNX_5/vhdl/
15	sample ucf file	jsauermann	7471d 08h	/c16/tags/Rev_XLNX_5/vhdl/
9	Made cpu_engine WISHBONE compliant. (Somebody please validate it).	jsauermann	7551d 02h	/c16/tags/Rev_XLNX_5/vhdl/
7	Handle auto variable declarations in compound statements properly	jsauermann	7559d 05h	/c16/tags/Rev_XLNX_5/vhdl/
2	no message	jsauermann	7563d 01h	/c16/tags/Rev_XLNX_5/vhdl/