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[/] [c16/] [tags/] [Rev_XLNX_7/] [vhdl/] - Rev 26

Rev	Log message	Author	Age	Path
26	New directory structure.	root	5564d 18h	/c16/tags/Rev_XLNX_7/vhdl/
22	This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_7'.		6924d 03h	/c16/tags/Rev_XLNX_7/vhdl/
21	Changes for Xilinx Proj. Nav. 7.1.02i	jsauermann	6924d 03h	/c16/tags/Rev_XLNX_7/vhdl/
19	FPGA Pin desription added.	jsauermann	7120d 00h	/c16/tags/Rev_XLNX_7/vhdl/
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7420d 23h	/c16/tags/Rev_XLNX_7/vhdl/
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7420d 23h	/c16/tags/Rev_XLNX_7/vhdl/
15	sample ucf file	jsauermann	7460d 02h	/c16/tags/Rev_XLNX_7/vhdl/
9	Made cpu_engine WISHBONE compliant. (Somebody please validate it).	jsauermann	7539d 21h	/c16/tags/Rev_XLNX_7/vhdl/
7	Handle auto variable declarations in compound statements properly	jsauermann	7547d 23h	/c16/tags/Rev_XLNX_7/vhdl/
2	no message	jsauermann	7551d 19h	/c16/tags/Rev_XLNX_7/vhdl/