URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] [c16/] [trunk/] [vhdl/] - Rev 30

Rev	Log message	Author	Age	Path
26	New directory structure.	root	5565d 15h	/c16/trunk/vhdl/
25	XOR bug fixed	jsauermann	6623d 22h	/trunk/vhdl/
23	Fixed problem with wishbone wait-states	jsauermann	6924d 19h	/trunk/vhdl/
21	Changes for Xilinx Proj. Nav. 7.1.02i	jsauermann	6925d 01h	/trunk/vhdl/
19	FPGA Pin desription added.	jsauermann	7120d 21h	/trunk/vhdl/
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7421d 20h	/trunk/vhdl/
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7421d 21h	/trunk/vhdl/
15	sample ucf file	jsauermann	7461d 00h	/trunk/vhdl/
9	Made cpu_engine WISHBONE compliant. (Somebody please validate it).	jsauermann	7540d 18h	/trunk/vhdl/
7	Handle auto variable declarations in compound statements properly	jsauermann	7548d 20h	/trunk/vhdl/
2	no message	jsauermann	7552d 17h	/trunk/vhdl/