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Rev Log message Author Age Path
161 New directory structure. root 5572d 06h /can/tags/rel_23/sim/
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7168d 14h /can/tags/rel_23/sim/
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7334d 10h /can/tags/rel_23/sim/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7559d 05h /can/tags/rel_23/sim/
119 Artisan RAMs added. mohor 7600d 16h /can/tags/rel_23/sim/
48 Actel APA ram supported. mohor 7772d 03h /can/tags/rel_23/sim/
35 Several registers added. Not finished, yet. mohor 7787d 06h /can/tags/rel_23/sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7792d 07h /can/tags/rel_23/sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7792d 23h /can/tags/rel_23/sim/
25 *** empty log message *** mohor 7797d 11h /can/tags/rel_23/sim/
24 backup. mohor 7802d 01h /can/tags/rel_23/sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7817d 13h /can/tags/rel_23/sim/
16 rx_fifo is now working. mohor 7818d 14h /can/tags/rel_23/sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7823d 04h /can/tags/rel_23/sim/
13 Temporary files (backup). mohor 7823d 11h /can/tags/rel_23/sim/
11 Acceptance filter added. mohor 7825d 00h /can/tags/rel_23/sim/
8 Testbench define file added. Clock divider register added. mohor 7837d 10h /can/tags/rel_23/sim/
5 Synchronization working. mohor 7838d 12h /can/tags/rel_23/sim/
4 Dir keeper. mohor 7843d 09h /can/tags/rel_23/sim/
2 Initial mohor 7843d 09h /can/tags/rel_23/sim/

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