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[/] [cpu65c02_true_cycle/] - Rev 23

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23 Added "beta" section to separate upcoming beta versions or release candidates from released versions.
The currently released version moved to "released".
The upcoming v2.00rc loaded into "beta" is a major release candidate containing performance improvements.
fmax is now typical from 110 MHz to 180 MHz even for low/middle cost FPGA devices. High end FPGA devices allow clock rates over 250 MHz now.
After many cycle count issues caused by description errors in original vendor documents, the v2.00rc testing processes (in progress) rely on the WDC 65C02 documentation and physical chips for reference now.		 fpga_is_funny 2058d 07h /cpu65c02_true_cycle/
22 v1.52 PRODUCTION
RESET generates SYNC now, 1 dead cycle delayed		 fpga_is_funny 2092d 11h /cpu65c02_true_cycle/
21 fpga_is_funny 2093d 09h /cpu65c02_true_cycle/
20 fpga_is_funny 2093d 09h /cpu65c02_true_cycle/
19 fpga_is_funny 3957d 13h /cpu65c02_true_cycle/
18 RELEASE CANDIDATE V1.5 RC of r65c02_tc.
Major Bug Fixes are available.
Look at the header of r65c02_tc.vhd to get more details.
Because of translation errors made by a third party conversion tool in the past, Verilog sources are no longer available. May be re-activated in the future.

The upcoming PRODUCTION version will be include some enhancements for speed and resource utilization.		 fpga_is_funny 3957d 14h /cpu65c02_true_cycle/
17 Added old uploaded documents to new repository. root 5563d 09h /cpu65c02_true_cycle/
16 Added old uploaded documents to new repository. root 5564d 02h /cpu65c02_true_cycle/
15 New directory structure. root 5564d 02h /cpu65c02_true_cycle/

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