OpenCores
URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

Subversion Repositories cpu_lecture

[/] [cpu_lecture/] [trunk/] [src/] - Rev 25

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
25 uart transmitter state handling improved jsauermann 5182d 22h /cpu_lecture/trunk/src/
24 write updated SP in interrupt opcode jsauermann 5206d 21h /cpu_lecture/trunk/src/
23 fixed bugs in interrupt vector jsauermann 5208d 00h /cpu_lecture/trunk/src/
22 aligned I/O port numbers to real mega8 jsauermann 5208d 05h /cpu_lecture/trunk/src/
21 fixed bug in Sign bit computation for SUB and CP instructions jsauermann 5209d 23h /cpu_lecture/trunk/src/
20 readability of 95xx instructions improved jsauermann 5241d 20h /cpu_lecture/trunk/src/
19 another bug in the decoding of two-cycle instructions fixed jsauermann 5241d 20h /cpu_lecture/trunk/src/
18 fixed a bug that caused double execution of some 95xx instructions jsauermann 5244d 23h /cpu_lecture/trunk/src/
17 fixed missing carry flag for ROR instruction jsauermann 5248d 21h /cpu_lecture/trunk/src/
16 fixed missing RD_M signal for IN instruction jsauermann 5257d 22h /cpu_lecture/trunk/src/
15 fixed SP auto inc/dec problem jsauermann 5258d 00h /cpu_lecture/trunk/src/
14 fixed wrong Q_RSEL for LDD instruction jsauermann 5259d 20h /cpu_lecture/trunk/src/
13 fixed fault in LDD/STD decoding jsauermann 5260d 20h /cpu_lecture/trunk/src/
12 fixed bug in decoding of I/O address for SP jsauermann 5261d 21h /cpu_lecture/trunk/src/
11 fixed fault is BSET/BCLR instruction jsauermann 5263d 21h /cpu_lecture/trunk/src/
10 wait decoder fault fixed jsauermann 5264d 02h /cpu_lecture/trunk/src/
6 support multiple port sizes in make_mem jsauermann 5265d 04h /cpu_lecture/trunk/src/
2 initial check-in jsauermann 5269d 23h /cpu_lecture/trunk/src/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.