URL https://opencores.org/ocsvn/csa/csa/trunk

Subversion Repositories csa

[/] [csa/] [trunk/] [sw_sim/] - Rev 52

Rev	Log message	Author	Age	Path
52	add the macro DEBUG_OUTPUT for the general debug information output	simon111	5166d 08h	/csa/trunk/sw_sim/
49	group_decrypt module simulate success	simon111	5522d 22h	/csa/trunk/sw_sim/
48	improve key_schedule module	simon111	5527d 22h	/csa/trunk/sw_sim/
43	improve group_decrypt module	simon111	5532d 00h	/csa/trunk/sw_sim/
42	add group_decrypt module	simon111	5532d 06h	/csa/trunk/sw_sim/
41	add three moudule ts_serial_out ts_sync key_cnt	simon111	5532d 19h	/csa/trunk/sw_sim/
40	add timescale.v file and fix a bug in key_schedule module	simon111	5532d 23h	/csa/trunk/sw_sim/
34	add binary test date (only sw_sim now )	simon111	5534d 10h	/csa/trunk/sw_sim/
24	New directory structure.	root	5572d 15h	/csa/trunk/sw_sim/
22	decrypt module testbench update	simon111	5695d 22h	/trunk/sw_sim/
20	finished the stream_cypher module, this module passed modelsim , but doesn't pass veriwell, i don't know why	simon111	5709d 20h	/trunk/sw_sim/
18	try to add decrypt module (not finished yet)	simon111	5719d 22h	/trunk/sw_sim/
17	finish block_decypher module	simon111	5771d 04h	/trunk/sw_sim/
16	add the block_perm and block_sbox	simon111	5774d 20h	/trunk/sw_sim/
15	finished key_schedule module	simon111	5778d 22h	/trunk/sw_sim/
13	add key_schedule module(note: this module is not right yet)	simon111	5779d 22h	/trunk/sw_sim/
10	add the sw simulate stuff for key_perm	simon111	5812d 23h	/trunk/sw_sim/