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[/] [dbg_interface/] [tags/] [rel_20/] [bench/] - Rev 158

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Rev Log message Author Age Path
158 root 5558d 16h /dbg_interface/tags/rel_20/bench/
130 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7422d 17h /dbg_interface/tags/rel_20/bench/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7425d 01h /dbg_interface/tags/rel_20/bench/
124 Display for VATS added. mohor 7429d 21h /dbg_interface/tags/rel_20/bench/
121 Port signals are all set to zero after reset. mohor 7432d 22h /dbg_interface/tags/rel_20/bench/
120 test stall_test added. mohor 7433d 00h /dbg_interface/tags/rel_20/bench/
117 Define name changed. mohor 7434d 21h /dbg_interface/tags/rel_20/bench/
116 Data latching changed when testing WB. mohor 7434d 21h /dbg_interface/tags/rel_20/bench/
115 More debug data added. mohor 7435d 01h /dbg_interface/tags/rel_20/bench/
114 CRC generation iand verification in bench changed. mohor 7435d 02h /dbg_interface/tags/rel_20/bench/
113 IDCODE test improved. mohor 7435d 04h /dbg_interface/tags/rel_20/bench/
112 dbg_tb_defines.v not used. mohor 7435d 22h /dbg_interface/tags/rel_20/bench/
111 Define tap_defines.v added to test bench. mohor 7435d 22h /dbg_interface/tags/rel_20/bench/
110 Waiting for "ready" improved. mohor 7435d 23h /dbg_interface/tags/rel_20/bench/
102 New version. mohor 7437d 18h /dbg_interface/tags/rel_20/bench/
101 Almost finished. mohor 7437d 19h /dbg_interface/tags/rel_20/bench/
99 cpu registers added. mohor 7438d 21h /dbg_interface/tags/rel_20/bench/
96 Working. mohor 7440d 01h /dbg_interface/tags/rel_20/bench/
95 Temp version. mohor 7440d 13h /dbg_interface/tags/rel_20/bench/
93 tmp version. mohor 7442d 00h /dbg_interface/tags/rel_20/bench/

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