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[/] [dbg_interface/] [tags/] [rel_5/] [sim/] - Rev 158

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Rev Log message Author Age Path
158 root 5564d 20h /dbg_interface/tags/rel_5/sim/
62 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7614d 02h /dbg_interface/tags/rel_5/sim/
36 Structure changed. Hooks for jtag chain added. mohor 8124d 01h /dbg_interface/tags/rel_5/sim/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8264d 04h /dbg_interface/tags/rel_5/sim/
5 Trace fixed. Some registers changed, trace simplified. mohor 8295d 02h /dbg_interface/tags/rel_5/sim/
2 Initial official release. mohor 8300d 02h /dbg_interface/tags/rel_5/sim/

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