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[/] [dblclockfft/] [trunk/] [rtl/] - Rev 43

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Rev Log message Author Age Path
43 Adjusted ignore properties dgisselq 1910d 18h /dblclockfft/trunk/rtl/
39 Updated Verilog, added window function demo dgisselq 1910d 18h /dblclockfft/trunk/rtl/
36 Added several new modes to the FFT

This makes the FFT core generator a generator for a generic
pipelined FFT--whether it be two samples per clock, one
sample per clock, one sample per two clocks, or even one
sample every three clocks.

This version works in simulation, with some formal checks
as well.
dgisselq 2169d 23h /dblclockfft/trunk/rtl/

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