| Rev |
Log message |
Author |
Age |
Path |
| 26 |
A lot of updates and upgrades in this release. Specifically, work took place
over the last several days to demonstrate this FFT on an FPGA. It was
demonstrated on the Xilinx Artix-7 found on a Basys-3 development board.
Part of the effort stemmed around making certain that the DSPs were used
optimally, part of it stemmed around making certain that various parts of the
FFT could use block RAM-type memories. The other massive change involved
removing as much unnecessary logic as possible, so that two 16-bit 1k FFTs
could fit onto this part--together with other glue logic. The bottom line,
though, is that it all now works. Specifically, I've tested it successfully
with
fftgen -f <FFTSIZE> -n 16 -m 16 -p 7 -c 1 -x 1
and with FFTSIZEs of 32, 64, 128, 256, 512, and 1024.
Oh, I should mention that there's also an undocumented DEBUG interface to the
part, and I fixed where the Verilog files went when given an argument, so
that they actually went to the directory specified. Minor updates have taken
place to the documentation format, making it match the documentation format
for other opencores projects that I've produced.
On a sadder note, the Verilator simulation fft_tb no longer works. (Yeah, get
that---the FFT implementation works but Verilator does not. Sigh). |
dgisselq |
3287d 22h |
/dblclockfft/trunk/sw/ |
| 25 |
The documentation has been changed to bring it closer to the example
specification document. The big change is that the first line, the
headline if you will, of each table has een adjusted to have a gray
background.
The second and bigger change is in the fftgen software itself, or more
specifically to the code that it produces. I had the opportunity to build
the code using Xilinx's ISE and spent some time getting rid of warnings
during the build. As a result, registers that need initial conditions
now have initial conditions. In a similar manner I have trimmed out
registers that were unused. The resulting code continues to pass all
test benches, although I will admit that the automated testing of the
whole fft or ifft via there test benches, fft_tb and ifft_tb, continues
to be a less than automated process than it should be. Therefore, these
test benches always "pass" and only a manual examination of the results
can be used to confirm their success. |
dgisselq |
3337d 22h |
/dblclockfft/trunk/sw/ |
| 24 |
Found some bugs in the synchronization code, such that if a reset was
issued residual internal synchronization signals might not get cleared.
These have been fixed.
Other updates have been made to the internal source documentation. |
dgisselq |
3357d 20h |
/dblclockfft/trunk/sw/ |
| 23 |
Lot's of work to implement a variable means of rounding. The variable
rounding is now implemented within the code, all that's left is to
place a command line option to the generator to choose how values
are to be rounded: either by truncation (drop the lower bits), by
always rounding half up (if the first extra bit is one, go up),
by rounding away from zero (if exactly .5, move away from zero), or
by rounding towards even (if exactly .5, move towards the nearest
even value).
This added an extra clock cycle to each stage, so all of the
test benches needed to be reworked. There is currently no testbench
to test the rounding method itself. This necessitated some
wholescale changes to the testbench code, and the addition
of the twoc.[h|cpp] files. (They were within every piece of code, just
copied from one to the next, this now encapsulates them within their
own file so fixes will propagate to all.) Other changes include creating
testbench classes, adjusting the classes so that one can test what will
happen if the sync isn't added initially, and more. In the end, my
problem was tied to an assumption within fftmain.v that dblstage would
always be a one tick delay, whereas with the one tick of the rounding
function it now becomes a two tick delay .... but the task is done, and
the FFT appears to work again. The maximum sum of square errors (XISQ)
is about half what it was before now, when I use convergent rounding. |
dgisselq |
3367d 12h |
/dblclockfft/trunk/sw/ |
| 22 |
Lot's of changes, mostly around getting this multiply to fit within a
particular FPGA. Specifically, we just added the capability of using
hardware multiplies to the command line options. Use them if you have
them, and it will simplify the operation of the FFT. |
dgisselq |
3368d 15h |
/dblclockfft/trunk/sw/ |
| 21 |
Modified the core generator so that the result compiles with Xilinx's Vivado
toolsuite without generating any syntax errors. |
dgisselq |
3369d 10h |
/dblclockfft/trunk/sw/ |
| 20 |
Adjusted rounding to use the floating point modes inherent in the double type.
Hence, (int)(x+0.5) has been replaced by (int)round(x). |
dgisselq |
3371d 01h |
/dblclockfft/trunk/sw/ |
| 19 |
Added the capability to accumulate bits internal to the FFT, only to drop
those extra bits just before the end. This helps to reduce truncation
error, and may even drop it by a factor of four (my own measurements). |
dgisselq |
3371d 20h |
/dblclockfft/trunk/sw/ |
| 16 |
Cleaned up the test bench build scripts, made sure license statements were
placed on all files, etc. |
dgisselq |
3373d 13h |
/dblclockfft/trunk/sw/ |
| 15 |
Added rounding into the routine to remove bias. All of the test benches have
been modified so that the FFT, with rounding, now passes. While the rounding
implementation applied does remove bias, it does not yet remove all bias.
Some work still remains. |
dgisselq |
3374d 11h |
/dblclockfft/trunk/sw/ |
| 14 |
Found several bugs in the previous version. The biggest were in the qtrstage.
Apparently, the qtrstage didn't work before, even though I thought it did.
Further, the FFT testbench has been adjusted to place proper values into
the fft_tb.dbl file it creates. (I've been testing it by reading this into
Octave, and visually inspecting the results--quantitative testing of the
fft_tb and ifft_tb are still lacking.) Now, however, if I cascade the
forward and reverse together, I seem to get something at least close to the
right answer. Close, of course, is relative. I think all that I still
struggle with is rounding and truncation errors, hence I'm checking in
my changes.
The FFT generator was also modified to allow arbitrary length paths
in the command line specified path prefix. This has not been tested.
A bug was also found in the butterfly, whereby for certain multiply delays
the butterfly would be unable to determine whether or not its results were
valid. Adding an extra bit to the FIFO address in these cases fixed the
problem. This change was encapsulated into the lgdelay() function, and
an additional bflydelay function. In my frustration, I modified the
fftstage function so that, when it is built, the parameters it is built
with are the default parameters. This should only affect testing, by
making any testing more realistic, but that may still remain to be seen.
Another change was made to the core generator, so that now when a core
is generated, the main file now contains a copy of the arguments that were
used when the core generator was invoked. This is good for posterity, in
case you ever need to ask yourself how I ended up here. |
dgisselq |
3375d 10h |
/dblclockfft/trunk/sw/ |
| 9 |
Now working on the test bench for the FFT. Currently, the FFT passes
all test bench "tests." However, the test bench does not yet accurately
report on the success of its work. This remains for future work. Lots
of bugs fixed while making this test bench code work.
(I should mention, while all test benches currently pass, that doesn't
mean that the code works ... yet. I just haven't found the bug that
breaks it.) |
dgisselq |
3381d 15h |
/dblclockfft/trunk/sw/ |
| 8 |
This completes the initial work on a test bench for the FFT stage. I
chose to test the odd 2048 stage only, but (hopefully) the testbench
will still apply to all other stages as well. At any rate, based upon
some trial runs, it looks like the FFT may be starting to work as well.
More testing is needed, for certain, but to do that I'm going to have
to figure out just what tests are needed, and how exactly to apply those
tests within the test bench construct. |
dgisselq |
3381d 22h |
/dblclockfft/trunk/sw/ |
| 6 |
Lots of work accomplished today. Test benches now exist and work for the:
butterfly, multiply, bitreversal, pairwise FFT stage (dblstage), and the
four-wise FFT stage (qtrstage). Work continues on the single (generic)
FFT stage, and (of course) the FFT isn't ready yet. A second commit will
follow this one shortly with the new files added (oops!--I should've added
them this time--my bad.) |
dgisselq |
3382d 09h |
/dblclockfft/trunk/sw/ |
| 5 |
The butterfly_tb is now written, and the butterfly succeeds at the test
bench! |
dgisselq |
3382d 16h |
/dblclockfft/trunk/sw/ |
| 3 |
The first upload of the s/w didn't take. Had it taken, the comment would've
been: This is the first upload of the double clocked FFT software. While it
should (roughly) be complete, a lot of work remains to be done--primarily
in building test benches, modifying the interface of fftgen to make it
more friendly, etc. In fact, the c++ code not only compiles, but the
Verilog code it produces actually builds as well!
Now, however, I have several test benches written, and have verified the
unit functionality of the multiply, bit reversal stage, the dblstage (FFT
len 2), and the qtrstage (FFT len 4). I then took a closer look at the
multiply, discovered it failed at signed integers and rebuilt it. The
new test bench tests the full 16-bit signed integer support properly. This
leaves butterflies and generic FFT stages that still need test benches, as
does the main (I)FFT program. |
dgisselq |
3382d 22h |
/dblclockfft/trunk/sw/ |
| 2 |
Here's an attempt at a first subversion update. |
dgisselq |
3382d 22h |
/dblclockfft/trunk/sw/ |
