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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 354

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Rev Log message Author Age Path
354 Whitespace cleanup olof 4687d 22h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4690d 00h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4694d 05h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4702d 19h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4702d 20h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4703d 21h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4704d 22h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4714d 22h /ethmac/trunk/rtl/verilog/
338 root 5509d 01h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 5566d 06h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 7014d 20h /ethmac/trunk/rtl/verilog/
332 Case statement improved for synthesys. igorm 7028d 01h /ethmac/trunk/rtl/verilog/
330 Warning fixes. igorm 7043d 03h /ethmac/trunk/rtl/verilog/
329 Defer indication fixed. igorm 7043d 04h /ethmac/trunk/rtl/verilog/
328 Delayed CRC fixed. igorm 7043d 04h /ethmac/trunk/rtl/verilog/
327 Defer indication fixed. igorm 7043d 05h /ethmac/trunk/rtl/verilog/
326 Delayed CRC fixed. igorm 7043d 05h /ethmac/trunk/rtl/verilog/
325 Defer indication fixed. igorm 7043d 05h /ethmac/trunk/rtl/verilog/
323 Accidently deleted line put back. igorm 7340d 05h /ethmac/trunk/rtl/verilog/
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7344d 00h /ethmac/trunk/rtl/verilog/

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