OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 366

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
366 Readded eth_top.v with a deprecation warning olof 4679d 22h /ethmac/trunk/rtl/verilog/
365 Whitespace cleanup olof 4680d 21h /ethmac/trunk/rtl/verilog/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4681d 19h /ethmac/trunk/rtl/verilog/
360 Added partial implementation of the debug register from ORPSoC olof 4683d 02h /ethmac/trunk/rtl/verilog/
359 Verilator linting fixes olof 4685d 04h /ethmac/trunk/rtl/verilog/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4686d 18h /ethmac/trunk/rtl/verilog/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4686d 19h /ethmac/trunk/rtl/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4686d 20h /ethmac/trunk/rtl/verilog/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4686d 21h /ethmac/trunk/rtl/verilog/
354 Whitespace cleanup olof 4686d 22h /ethmac/trunk/rtl/verilog/
353 Inherit fixes for bit width of constants from ORPSoC olof 4688d 23h /ethmac/trunk/rtl/verilog/
352 Removed delayed assignments from rtl code olof 4693d 05h /ethmac/trunk/rtl/verilog/
351 Turn defines into parameters in eth_cop olof 4701d 19h /ethmac/trunk/rtl/verilog/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4701d 19h /ethmac/trunk/rtl/verilog/
349 Make all parameters configurable from top level olof 4702d 20h /ethmac/trunk/rtl/verilog/
346 Updated project location olof 4703d 22h /ethmac/trunk/rtl/verilog/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4713d 22h /ethmac/trunk/rtl/verilog/
338 root 5508d 00h /ethmac/trunk/rtl/verilog/
335 New directory structure. root 5565d 05h /ethmac/trunk/rtl/verilog/
333 Some small fixes + some troubles fixed. igorm 7013d 19h /ethmac/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.