URL https://opencores.org/ocsvn/manchesterwireless/manchesterwireless/trunk

Subversion Repositories manchesterwireless

[/] [manchesterwireless/] - Rev 14

Rev	Log message	Author	Age	Path
14	Removed Xilinx warning caused by missing signals in sensitivity list	kingmu	5455d 07h	/manchesterwireless/
13	Merged rewrite of singleDouble into trunk	kingmu	5456d 05h	/manchesterwireless/
12	Trivial updates	kingmu	5462d 11h	/manchesterwireless/
11	This is a perl model which functionally simulates manchester encoding and decoding.	thiagu_comp	5463d 21h	/manchesterwireless/
10	This folder contains the perl model, which functionally simulates manchester encoding and decoding. This can be used to validate the HDL model.	thiagu_comp	5463d 21h	/manchesterwireless/
9	Modified next state logic to avoid gated clock on net clock_zero_en_0000 during bitgen process. As a default case the counter enables are de-asserted.	thiagu_comp	5466d 22h	/manchesterwireless/
8	Removed old singleDouble and added .ucf	kingmu	5470d 00h	/manchesterwireless/
7	Added new singleDouble files	kingmu	5470d 00h	/manchesterwireless/
6	Branching trunk to experiment with new singleDouble module	kingmu	5470d 01h	/manchesterwireless/
5	Tagging 1.0 release	kingmu	5470d 10h	/manchesterwireless/
4	Updated simulation files to reflect new module names	kingmu	5475d 05h	/manchesterwireless/
3	Renamed files/modules. Added documentation.	kingmu	5475d 05h	/manchesterwireless/
2	initial commit	kingmu	5476d 06h	/manchesterwireless/
1	The project was created and the structure was created	root	5482d 21h	/manchesterwireless/