URL https://opencores.org/ocsvn/open_hitter/open_hitter/trunk

Subversion Repositories open_hitter

[/] [open_hitter/] [trunk/] - Rev 18

Rev	Log message	Author	Age	Path
18	search_control is up for simulation (ghdl)	stvhawes	3275d 06h	/open_hitter/trunk/
17	persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id	stvhawes	3280d 17h	/open_hitter/trunk/
16	minor fixes to search_control test bench	stvhawes	3287d 03h	/open_hitter/trunk/
15	adding in search_control and testbench	stvhawes	3288d 08h	/open_hitter/trunk/
14	search_item_wrapper bench debugged	stvhawes	3294d 04h	/open_hitter/trunk/
13	test bench for search_item	stvhawes	3297d 08h	/open_hitter/trunk/
12	wrapper test for search_item	stvhawes	3302d 18h	/open_hitter/trunk/
11	multiplex searh item added	stvhawes	3303d 11h	/open_hitter/trunk/
10	split source files to sime and rtl	stvhawes	3317d 10h	/open_hitter/trunk/
9	highlevel block diagram added	stvhawes	3318d 07h	/open_hitter/trunk/
8	sim sequence error fixed, so 20% success -> 100% success for unit test on fpga	stvhawes	3318d 09h	/open_hitter/trunk/
7	split clock/byte_ready and fix logic	stvhawes	3323d 02h	/open_hitter/trunk/
6	fixing synthesizable	stvhawes	3324d 11h	/open_hitter/trunk/
5	fixing synthesizable	stvhawes	3324d 15h	/open_hitter/trunk/
4	developing ideas around unit test / fpga verification	stvhawes	3325d 03h	/open_hitter/trunk/
3	developing ideas around unit test / fpga verification	stvhawes	3325d 03h	/open_hitter/trunk/
2	initial sources, wrappers for regression test harness	stvhawes	3336d 06h	/open_hitter/trunk/
1	The project and the structure was created	root	3338d 00h	/open_hitter/trunk/