URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [bench/] - Rev 33

Rev	Log message	Author	Age	Path
33	Fixed the network receive CRC and MAC checking, and added ip-checking and minimum packet length checking to the receiver.	dgisselq	2788d 05h	/openarty/trunk/bench/
32	Brought the CPU to its first working version, to include demo.	dgisselq	2789d 08h	/openarty/trunk/bench/
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2790d 01h	/openarty/trunk/bench/
28	Including the updates and corrections from the wbuart32 project.	dgisselq	2817d 22h	/openarty/trunk/bench/
15	These files were changed/perfected as part of getting the EQSPI flash driver up and running. They currently match the hardware, as far as I can tell, and the test bench (_tb.cpp file) shows that the Verilog modules work (with the simulated hardware) as designed.	dgisselq	2857d 02h	/openarty/trunk/bench/
11	Files necessary to simulate the entire Arty board--everything at the fastmaster module and below.	dgisselq	2858d 05h	/openarty/trunk/bench/
10	Updated flash data and test files, for a flash that produces it's answers a clock after I'm expecting them.	dgisselq	2858d 05h	/openarty/trunk/bench/
9	Adding copywrite statement (oops).	dgisselq	2858d 05h	/openarty/trunk/bench/
8	Fixes the makefile so it builds a complete testbench suite, emulating the entire Arty board.	dgisselq	2858d 05h	/openarty/trunk/bench/
5	Initial checkin, this time of the bench testing s/w.	dgisselq	2873d 08h	/openarty/trunk/bench/