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[/] [openarty/] [trunk/] [bench/] [cpp/] - Rev 34

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Rev Log message Author Age Path
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2783d 12h /openarty/trunk/bench/cpp/
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2788d 18h /openarty/trunk/bench/cpp/
32 Brought the CPU to its first working version, to include demo. dgisselq 2789d 21h /openarty/trunk/bench/cpp/
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2790d 13h /openarty/trunk/bench/cpp/
28 Including the updates and corrections from the wbuart32 project. dgisselq 2818d 10h /openarty/trunk/bench/cpp/
15 These files were changed/perfected as part of getting the EQSPI flash driver
up and running. They currently match the hardware, as far as I can tell, and
the test bench (_tb.cpp file) shows that the Verilog modules work (with the
simulated hardware) as designed.		 dgisselq 2857d 14h /openarty/trunk/bench/cpp/
11 Files necessary to simulate the entire Arty board--everything at the fastmaster
module and below.		 dgisselq 2858d 17h /openarty/trunk/bench/cpp/
10 Updated flash data and test files, for a flash that produces it's answers a
clock after I'm expecting them.		 dgisselq 2858d 17h /openarty/trunk/bench/cpp/
9 Adding copywrite statement (oops). dgisselq 2858d 17h /openarty/trunk/bench/cpp/
8 Fixes the makefile so it builds a complete testbench suite, emulating the
entire Arty board.		 dgisselq 2858d 17h /openarty/trunk/bench/cpp/
5 Initial checkin, this time of the bench testing s/w. dgisselq 2873d 20h /openarty/trunk/bench/cpp/

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