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[/] [openarty/] [trunk/] [sw/] - Rev 34

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Rev	Log message	Author	Age	Path
34	These updates bring the distribution along to the point where both the GPS clock subsecond tracking, as well as the OLEDrgb controller now work.	dgisselq	2776d 15h	/openarty/trunk/sw/
33	Fixed the network receive CRC and MAC checking, and added ip-checking and minimum packet length checking to the receiver.	dgisselq	2781d 21h	/openarty/trunk/sw/
32	Brought the CPU to its first working version, to include demo.	dgisselq	2783d 00h	/openarty/trunk/sw/
31	Initial network is now working. Adding CPU control files to repository.	dgisselq	2783d 17h	/openarty/trunk/sw/
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2783d 17h	/openarty/trunk/sw/
22	A useful script for programming the device, given that the current device program includes a valid comms interface.	dgisselq	2848d 17h	/openarty/trunk/sw/
18	The device can now program and configure itself, allowing bootstrap possibilities. `	dgisselq	2848d 17h	/openarty/trunk/sw/
16	This returns the scope to its original configuration, where the decode() function is not allowed to have any side effects.	dgisselq	2850d 17h	/openarty/trunk/sw/
14	All changes made as a part of getting the flash driver up and running. Today, it successfully programmed a configuration into the Arty via wbprogram, so ... that's been my last/best test.	dgisselq	2850d 18h	/openarty/trunk/sw/
6	Minor updates, mostly to support the development of the DDR3 SDRAM--such as creating addresses for the debugging scope used to figure out what's going on with it.	dgisselq	2851d 21h	/openarty/trunk/sw/
4	Initial host software pack.	dgisselq	2867d 00h	/openarty/trunk/sw/

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