OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] - Rev 178

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)
olivier.girard 4123d 03h /openmsp430/trunk/core/
175 Update hardware breakpoint unit with the followings:
- fixed hardware breakpoint bug with CALL instructions.
- modified data read watchpoint behavior to also trigger with read/modify/write instructions.
- removed unused ports.
olivier.girard 4140d 03h /openmsp430/trunk/core/
174 Cleanup dmem_wr generation logic. Important note: this is not a bug fix, only beautification. olivier.girard 4140d 03h /openmsp430/trunk/core/
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4247d 03h /openmsp430/trunk/core/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4332d 02h /openmsp430/trunk/core/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)
olivier.girard 4335d 04h /openmsp430/trunk/core/
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4385d 03h /openmsp430/trunk/core/
142 Beautify the linker script examples. olivier.girard 4406d 04h /openmsp430/trunk/core/
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4410d 03h /openmsp430/trunk/core/
139 Add some SVN ignore patterns olivier.girard 4422d 13h /openmsp430/trunk/core/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4422d 13h /openmsp430/trunk/core/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 4454d 04h /openmsp430/trunk/core/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4467d 03h /openmsp430/trunk/core/
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4475d 02h /openmsp430/trunk/core/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4551d 03h /openmsp430/trunk/core/
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.
olivier.girard 4623d 04h /openmsp430/trunk/core/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4727d 05h /openmsp430/trunk/core/
115 Add linker script example. olivier.girard 4752d 04h /openmsp430/trunk/core/
112 Modified comment. olivier.girard 4760d 04h /openmsp430/trunk/core/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4761d 04h /openmsp430/trunk/core/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.