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[/] [openmsp430/] [trunk/] [core/] [rtl/] - Rev 149

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149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)
olivier.girard 4335d 09h /openmsp430/trunk/core/rtl/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 4454d 09h /openmsp430/trunk/core/rtl/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4467d 08h /openmsp430/trunk/core/rtl/
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4475d 07h /openmsp430/trunk/core/rtl/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4551d 08h /openmsp430/trunk/core/rtl/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4727d 10h /openmsp430/trunk/core/rtl/
112 Modified comment. olivier.girard 4760d 09h /openmsp430/trunk/core/rtl/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4761d 09h /openmsp430/trunk/core/rtl/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 4817d 07h /openmsp430/trunk/core/rtl/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 4832d 08h /openmsp430/trunk/core/rtl/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 4837d 14h /openmsp430/trunk/core/rtl/
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+
olivier.girard 4838d 07h /openmsp430/trunk/core/rtl/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4838d 09h /openmsp430/trunk/core/rtl/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.
olivier.girard 4850d 09h /openmsp430/trunk/core/rtl/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4873d 06h /openmsp430/trunk/core/rtl/
85 Diverse RTL cosmetic updates. olivier.girard 4873d 08h /openmsp430/trunk/core/rtl/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.
olivier.girard 4878d 09h /openmsp430/trunk/core/rtl/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4939d 10h /openmsp430/trunk/core/rtl/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.
olivier.girard 5026d 09h /openmsp430/trunk/core/rtl/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5053d 10h /openmsp430/trunk/core/rtl/

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