Rev |
Log message |
Author |
Age |
Path |
154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4255d 09h |
/openmsp430/trunk/core/sim/rtl_sim/ |
151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4340d 08h |
/openmsp430/trunk/core/sim/rtl_sim/ |
149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4343d 10h |
/openmsp430/trunk/core/sim/rtl_sim/ |
145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4393d 09h |
/openmsp430/trunk/core/sim/rtl_sim/ |
142 |
Beautify the linker script examples. |
olivier.girard |
4414d 10h |
/openmsp430/trunk/core/sim/rtl_sim/ |
141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4418d 09h |
/openmsp430/trunk/core/sim/rtl_sim/ |
138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4430d 19h |
/openmsp430/trunk/core/sim/rtl_sim/ |
134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4462d 10h |
/openmsp430/trunk/core/sim/rtl_sim/ |
128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4559d 09h |
/openmsp430/trunk/core/sim/rtl_sim/ |
122 |
Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator. |
olivier.girard |
4631d 10h |
/openmsp430/trunk/core/sim/rtl_sim/ |
115 |
Add linker script example. |
olivier.girard |
4760d 11h |
/openmsp430/trunk/core/sim/rtl_sim/ |
111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4769d 10h |
/openmsp430/trunk/core/sim/rtl_sim/ |
106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4825d 08h |
/openmsp430/trunk/core/sim/rtl_sim/ |
105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4840d 09h |
/openmsp430/trunk/core/sim/rtl_sim/ |
103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4845d 15h |
/openmsp430/trunk/core/sim/rtl_sim/ |
102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4846d 08h |
/openmsp430/trunk/core/sim/rtl_sim/ |
101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4846d 10h |
/openmsp430/trunk/core/sim/rtl_sim/ |
99 |
Small fix for CVER simulator support. |
olivier.girard |
4850d 10h |
/openmsp430/trunk/core/sim/rtl_sim/ |
98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4850d 10h |
/openmsp430/trunk/core/sim/rtl_sim/ |
95 |
Update some test patterns for the additional simulator supports. |
olivier.girard |
4854d 10h |
/openmsp430/trunk/core/sim/rtl_sim/ |