Rev |
Log message |
Author |
Age |
Path |
154 |
The serial debug interface now supports the I2C protocol (in addition to the UART) |
olivier.girard |
4247d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
151 |
Add possibility to configure custom Program, Data and Peripheral memory sizes. |
olivier.girard |
4332d 06h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4335d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
141 |
Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) |
olivier.girard |
4410d 07h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4422d 18h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4454d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4551d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
122 |
Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator. |
olivier.girard |
4623d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4761d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4817d 07h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
99 |
Small fix for CVER simulator support. |
olivier.girard |
4842d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4842d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
94 |
Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim |
olivier.girard |
4846d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
76 |
Add possibility to simulate C code within the "core" environment. |
olivier.girard |
4944d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
73 |
Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell. |
olivier.girard |
5051d 09h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
72 |
Expand configurability options of the program and data memory sizes. |
olivier.girard |
5053d 10h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
65 |
Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. |
olivier.girard |
5211d 07h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
37 |
|
olivier.girard |
5268d 08h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5268d 10h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |
23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5389d 12h |
/openmsp430/trunk/core/sim/rtl_sim/bin/ |