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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] - Rev 202

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202 Add DMA interface support + LINT cleanup olivier.girard 3266d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3427d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3827d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4255d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4340d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)
olivier.girard 4343d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4418d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4430d 11h /openmsp430/trunk/core/sim/rtl_sim/bin/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 4462d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4559d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.
olivier.girard 4631d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4769d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 4825d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/
99 Small fix for CVER simulator support. olivier.girard 4850d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.
olivier.girard 4850d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim
olivier.girard 4854d 02h /openmsp430/trunk/core/sim/rtl_sim/bin/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4952d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.
olivier.girard 5059d 03h /openmsp430/trunk/core/sim/rtl_sim/bin/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5061d 03h /openmsp430/trunk/core/sim/rtl_sim/bin/
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5219d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/

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