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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] - Rev 94

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94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4846d 11h /openmsp430/trunk/core/sim/rtl_sim/bin/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4944d 11h /openmsp430/trunk/core/sim/rtl_sim/bin/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5051d 12h /openmsp430/trunk/core/sim/rtl_sim/bin/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5053d 13h /openmsp430/trunk/core/sim/rtl_sim/bin/
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5211d 10h /openmsp430/trunk/core/sim/rtl_sim/bin/
37 olivier.girard 5268d 11h /openmsp430/trunk/core/sim/rtl_sim/bin/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5268d 14h /openmsp430/trunk/core/sim/rtl_sim/bin/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5389d 15h /openmsp430/trunk/core/sim/rtl_sim/bin/
17 Updated header with SVN info olivier.girard 5415d 11h /openmsp430/trunk/core/sim/rtl_sim/bin/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5450d 10h /openmsp430/trunk/core/sim/rtl_sim/bin/

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